1. Field of the Invention
The technology described herein relates to non-volatile memory.
2. Description of the Related Art
Semiconductor memory has become more popular for use in various electronic devices. For example, non-volatile semiconductor memory is used in cellular telephones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices and other devices. Electrical Erasable Programmable Read Only Memory (EEPROM) and flash memory are among the most popular non-volatile semiconductor memories.
Both EEPROM and flash memory utilize a floating gate that is positioned above and insulated from a channel region in a semiconductor substrate. The floating gate is positioned between the source and drain regions. A control gate is provided over and insulated from the floating gate. The threshold voltage of the transistor is controlled by the amount of charge that is retained on the floating gate. That is, the minimum amount of voltage that must be applied to the control gate before the transistor is turned on to permit conduction between its source and drain is controlled by the level of charge on the floating gate.
When programming an EEPROM or flash memory device, such as a NAND flash memory device, typically a program voltage is applied to the control gate and the bit line is grounded. Electrons from the channel are injected into the floating gate. When electrons accumulate in the floating gate, the floating gate becomes negatively charged and the threshold voltage of the memory cell is raised so that the memory cell is in a programmed state. More information about programming can be found in U.S. Pat. No. 6,859,397 and U.S. Pat. No. 6,917,542; both of which are incorporated herein by reference in their entirety.
Typically, the program voltage applied to the control gate is applied as a series of pulses. The magnitude of the pulses is increased with each pulse by a predetermined step size. In the periods between the pulses, verify operations are carried out. That is, the programming level of each memory cell being programmed in parallel is read between each programming pulse to determine whether it is equal to or greater than a verify level to which it is being programmed. One means of verifying the programming is to test conduction between the memory cell's source and drain at a specific compare point.
Conduction represents an “on” state of the device corresponding to the flow of current across the channel of the device. An “off” state corresponds to no current flowing across the channel between the source and drain. Typically, a flash memory cell will conduct if the voltage being applied to the control gate is greater than the threshold voltage and the memory cell will not conduct if the voltage applied to the control gate is less than the threshold voltage. By setting the threshold voltage of the memory cell to an appropriate value, the memory cell can be made to either conduct or not conduct current for a given set of applied voltages. Thus, by determining whether a memory cell conducts current at a given set of voltages, the state of the memory cell can be determined.
Flash memory cells are erased by raising the p-well to an erase voltage (e.g. 20 volts) and grounding the word lines of a selected block (or other unit) of memory cells. The source and bit lines are floating. Erasing can be performed on the entire memory array, separate blocks, or another unit of cells. Electrons are transferred from the floating gate to the p-well region and the threshold voltage becomes negative.
Some flash memory systems use group the memory cells into an array, organized so that a set of bit lines and word lines can be used to address a particular memory cell. In one example, the memory cells are grouped into a set of NAND strings. Each NAND string includes multiple transistors in series between two select gates (a drain side select gate SGD and a source side select gate SGS). In typical read and verify operations for NAND flash memory, the select gates (SGD and SGS) are raised to approximately 3 volts and the unselected word lines are raised to a read pass (or enable) voltage (e.g. 5 volts) to make the transistors operate as pass gates. The selected word line is connected to a compare voltage, a level of which is specified for each read or verify operation in order to determine whether a threshold voltage of the concerned memory cell has reached such level. The source and p-well are at zero volts. The selected bit lines are pre-charged to a level of, for example, 0.7V. If the threshold voltage is higher than the verify or read level applied to the selected word line, the potential level of the concerned bit line maintains the high level because of the non-conductive memory cell. On the other hand, if the threshold voltage is lower than the read or verify level, the potential level of the concerned bit line decreases to a low level, for example less than 0.5V, because of the conductive memory cell. The state of the memory cell is detected by a sense amplifier that is connected to the bit line.
Typically, in between read operations and in between program and verify operations the word lines are at 0 volts. The unselected word lines are raised to the read pass voltage at the same time as the selected word line is raised to the read compare voltage. Because the read pass voltage is generally much larger than the read compare voltage, the word lines are close together and the word lines can be relatively long, coupling noise can appear on the selected word line when it is raised to the read compare voltage while the unselected word lines are raised to the read pass voltage. This coupling initially raises the voltage of the selected word line; however, the raised voltage will dissipate over time so that the selected word line settles at the intended read compare voltage. To avoid errors, some systems will need to delay the read process in order to wait for the selected word line to settle at the intended read compare voltage. This waiting slows down the reading and/or verification process.
One proposal to remedy the coupling issue described above is to slow down the ramp-up of the read pass voltage on the unselected word lines. However, this solution also slows down the reading and verification process.
Another proposal is to reduce the capacitive coupling of the word lines. However, to reduce the capacitive coupling of the word lines more expensive materials need to be used or die size needs to be increased in order to increase space in between word lines.
Another proposal is to maintain the word lines at the read pass voltage in between read operations and in between program and verify operations. Therefore, the unselected word lines would not need to be ramped up during a read process. A problem with this approach is that to move the word lines to the read pass voltage from other voltages using during the programming process (or other processes) requires a charge pump or other circuit to sink a large amount of current to bring down the word lines to the read pass voltage. For example, during a program-verify process, the word lines must move from a boosting voltage (e.g. 10 volts) to the read pass voltage (e.g., approximately 5 volts). Some charge pumps and other circuit typically found on flash memory device today cannot efficiently sink current to bring the voltage down to any specific voltages except for standby voltage. New circuits for more complicated sequence and voltage detection control may need to be added that itself will require additional space on the device.